1. Field of the Invention
The present invention relates to a zero detection circuit used in an electronic calculator or computer and more specifically to a zero detection circuit for detecting zero for all bits in a result of addition or subtraction between a pair of binary numbers.
2. Description of Related Art
Hitherto, so-called zero detection circuits have been used for detecting that a result of addition or subtraction between a pair of binary numbers composed of the same numbers of bits is zero from its most significant bit (MSB) to its least significant bit (LSB).
The zero detection has been executed as follows. The pair of binary numbers are added or subtracted to each other by an addition circuit or a subtraction circuit for each digit or place in the order counted from their LSB bit to their MSB bit, and the result of addition or subtraction for each digit is inputted to a NOR circuit. When the addition or subtraction has been completed from the LSB bit to the MSB bit, if the NOR circuit finally outputs a logic value "1", it is detected or judged that all bits of the result of addition or subtraction are zero.
In the above mentioned zero detection circuit, however, if the bit number of the binary numbers to be added or subtracted becomes large, the time from the start of the addition/subtraction to the completion of the addition/subtraction for the MSB bits becomes long. Therefore, the zero detection (the detection of all bits ="0") in the result of operation is correspondingly delayed. Namely, the efficiency of the zero detection becomes low.
Furthermore, the NOR circuit of the conventional zero detection circuit has been of a dynamic type in most cases. In the case that a dynamic NOR circuit is used, the zero detection of the addition/subtraction result has been performed as illustrated in the timing chart of FIG. 1.
Namely, the dynamic NOR circuit alternately repeats a precharge period t.sub.p and a sampling period t.sub.s in synchronism with a clock pulse as shown in FIG. 1. In the case of the addition, when the dynamic NOR circuit is in the sampling period, an addition output signal is inputted from an addition circuit to the dynamic NOR circuit with a delay time of t.sub.2 from the start of the sampling period t.sub.s, as shown in FIG. 1. This delay time t.sub.2 is determined by a total time of a carry propagation time from a LSB to a MSB and an addition time for the MSB. In addition, as illustrated in FIG. 1, the dynamic NOR circuit generates an output signal after a delay time t.sub.3 which is determined by the operation time of the dynamic NOR circuit itself.
As seen from the above, the conventional zero detection circuit has been such that when the sampling period is started, the zero detection is executed for the result of addition after a delay of (t.sub.2 +t.sub.3) in total from the start of the sampling period. Therefore, if the bit number of the binary numbers to be subjected to addition/subtraction becomes large, since the carry propagation time from the LSB to the MSB will inevitably increase, the delay time t.sub.2 will become large as a matter of course. Accordingly, the delay of the zero detection will become more pronounced. This problem will also occur in the case of detecting zero in a result of subtraction.